"Challenges of CIS High Parallel Test"
Larry Levy, FormFactor, USA
Few interesting slides from the presentation:
Comparison of CIS testing with others (TD is Touch Downs, "\\" stands for Parallelism):
Challenges of CIS Wafer-Level Testing
2011 IEEE Semiconductor Wafer Test Workshop held in San Diego, CA on June 12-15 has a presentation on CIS testing:
"Challenges of CIS High Parallel Test"
Larry Levy, FormFactor, USA
Few interesting slides from the presentation:
Comparison of CIS testing with others (TD is Touch Downs, "\\" stands for Parallelism):
"Challenges of CIS High Parallel Test"
Larry Levy, FormFactor, USA
Few interesting slides from the presentation:
Comparison of CIS testing with others (TD is Touch Downs, "\\" stands for Parallelism):
