The patented ADC is of the counting ramp type combined with CDS in the digital domain and said to result in very low FPN. The prior art ADC with digital CDS has up and down counter to subtract the reset level from the signal level:
CMOSIS patented solution only needs a counting in one direction, while the subtraction is achieved by changing the timing logic. There are two version of counting logic presented:
Another advantage of the proposed ADC logic is that the full conversion can be achieved with just one analog ramp. In that case the comparator offset can be controllably changed between the signal and reset samples and the same counter can be used:
There are more techniques described in the patent, such as its application for TDI, pulse stretching or shrinking and clock interpolation.