Toshiba Staggered Pixel Presented at ISSCC

Tech-On! describes Toshiba 8MP 1.75um pixel sensor, which Toshiba presents at ISSCC these days. The sensor uses two innovations: staggered pixels and floating diffusion boost. Staggered pixel idea is supposed to improve Gr/Gb mismatch and is shown below:



I'm not sure what happens with RST signal routing in this scheme, it looks like the wiring should be duplicated. It might be not an issue, if SEL transistor is eliminated. The staggered pixel is claimed to improve Gr/Gb ratio from 94.9% to 99.7%.

Another innovation is the FD voltage boost, apparently achieved through the source follower gate capacitance. This is a nice idea, albeit a bit obvious.

Toshiba plans to commercialize a product that uses staggered pixel layout and FD boost in spring 2009 at earliest.